Digital Verification Engineer
NXP Semiconductors N.V. enables secure connections for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 30,000 employees in more than 30 countries and posted revenue of $9.41 billion in 2018.
As a key member of the verification team, you will be responsible to:
- Review and understand the design requirements and specifications;
- Create, together with Digital Designers and SoC Architects, a verification plan;
- Complete and review the plan with details about execution priority and effort estimations;
- Execute the plan, at Block and/or SoC level, creating ad-hoc test-benches and simulation models or updating the existing ones;
- Code the expected test-cases and assertions;
- Interact with your peers, designers and architects for a quick analysis and resolution of all found bugs;
- Complete the verification execution with Code Coverage analysis and final reports;
- Maintain and develop the verification environment across the different projects, proposing improvements to both the methodology, ways of working, team praxis and tool-chain;
- Keep yourself updated with latest verification methodology updates by following courses, seminars, webinars and literature.
- Master Degree in Electrical or Electronic Engineering or similar;
- Good, proven knowledge of Verilog and System Verilog languages (VHDL is a plus);
- Experience in testbench design and development with standard verification frameworks like UVM;
- Good understanding of Metric Driven Verification concepts, functional and code coverage;
- Understanding of directed and constrained random methodologies;
- Knowledge of formal verification methodologies and assertions;
- Familiar with languages used for testcase development: C dialects, Linux Bash, Tcl (VBA, Python and/or Perl are a plus;
- Familiar with ASIC / SoC design flow and process (hands-on experience or RTL coding is a bonus).
NXP offers competitive compensation. Due to Austrian law we are obliged to state the minimum gross salary according to legal regulations and for this role this amounts to EUR 53.000 gross.
Depending on experience and education higher remuneration is possible. Moreover, we provide attractive benefits to our employees.
Please apply via career page or contact Spela Kremzer (firstname.lastname@example.org).